nxp displayport-to-dvi/ hdmi level shifters ptn3300/3300a/ 3300b/3301 key features 4 high-speed tmds level shifting up to 2.25 gbps per lane (225-mhz character clock) 4 ddc level shifting from 3.3 v (source) to 5 v (sink) with clock frequency from 0 to 400 khz 4 ddc active buffering and rise-time accelerator (ptn3301 only) 4 ddc dongle-detect feature (ptn3301 only) 4 hpd level shifting from 0 to 5 v (sink) to 0 to 3.3 v (source) 4 hpd inverting level shifting to 1.1 v (source; ptn3300a only) 4 integrated 50 - termination resistors for ac-coupled differential inputs 4 single power supply voltage of 3.3 v 10% 4 high esd resilience to 3.5 kv hbm, 1 kv cdm 4 pin-programmable power-saving mode disabling tmds and ddc channels 4 automatic power-saving mode upon hot plug detect (hpd) going low 4 back-current-safe design on all sink- side terminals applications 4 intel and amd motherboards with reconfgurable i/o for display interfaces 4 amd/ati and nvidia graphics cards with reconfgurable i/o for display interfaces 4 displayport-to-dvi and -hdmi dongles and cable assemblies 4 desktop and notebook motherboards with reconfgurable display interfaces these high-speed level shifters translate from displayport electrical signals to dvi and hdmi signals. the ptn3300 supports dvi and hdmi for motherboard and dongle applications up to 1.65 gbps. the ptn3300a adds an inverting hpd channel and supports speeds up to 2.25 gbps. the ptn3300b is a high-speed version of the ptn3300, supporting speeds up to 2.25 gbps. the ptn3301 adds active ddc buffering and rise-time acceleration, plus the hdmi dongle-detect feature. the level shifters let chipset vendors implement reconfgurable i/o on multimode display sources, and thereby support multiple display standards while keeping the number of chipset i/o pins low. when the chipset is confgured to dvi or hdmi, it outputs tmds-coded signals, while the chipset i/o pins employ ac-coupled pci express or displayport electrical levels. translation of the electrical levels is necessary because dvi and hdmi use dc-coupled, 3.3-v differential signaling. signal translation from pcie and displayport to dvi and hdmi to support the new, high-speed motherboard graphics chipsets from intel, amd/ati, nvidia, and others, these devices provide electrical-level translation from displayport signals to the current- mode outputs required to drive dvi and hdmi displays.
ptn3300/a/b the ptn3300/a/b converts four lanes of low-swing, ac-coupled, differential input signals to dvi-compliant, open-drain, current-steering differential output signals. it provides level shifting for each differential lane, and equips each differential output with advanced wave-shaping for optimal performance. the ptn3300 operates at up to 1.65 gbps, the ptn3300a and b versions operate at up to 2.25 gbps. the ptn3300a is identical to ptn3300b, with the exception that its hpd channel is a logic-inverter function, and level shifts, on the source side, to a 1.1-v level instead of a 3.3-v logic level. the ptn3300/a/b also supplies a single-ended, active buffer for voltage translation of the hpd signal, from 5 v on the sink side to 3.3 v on the source side. an integrated 200-k pull-down resistor on the hpd sink input guarantees input low when no display is plugged in. a ddc channel (clock and data lines) level shifts between 3.3 v on the source side and 5 v on the sink side. the ddc channel uses pass-gate technology, so it can level-shift and disable the clock and data lines, isolating the source from the sink. the ddc level shifting is back-power safe, to disallow back-drive current when the power is off or when ddc is not enabled. 002aad344 out_d1- out_d1+ in_d1- in_d1+ hpd_source hpd_sink scl_sink sda_sink ddc_en (0 v to 3.3 v) scl_source sda_source out_d2- out_d2+ in_d2- in_d2+ out_d3- out_d3+ in_d3- in_d3+ out_d4- out_d4+ in_d4- in_d4+ ptn3300/a/b oe_n dvi/hdmi connector 5 v 5 v 0 v to 5 v 0 v to 3.3 v 3.3 v 3.3 v 3.3 v ac-coupled differential pair clock clock lane data lane data lane data lane ac-coupled differential pair tmds data ac-coupled differential pair tmds data ac-coupled differential pair tmds data tx tx ff tmds clock pattern multi-mode display source tx tx ff tmds coded data tx tx ff tmds coded data tx tx ff tmds coded data pcie phy electrical configuration ddc i/o (i 2 c-bus) pcie output buffer reconfigurable i/os pcie output buffer pcie output buffer pcie output buffer application example, (except in case of ptn3300a, hpd_source is inverted and level shifted to 1.1 v) ptn3300a block diagram 002aad646 out_d1? out_d1+ input bias 50 50 in_d1? in_d1+ hpd level shifter hpd_source_n (0 v to 1.1 v) hpd_sink (0 v to 5 v) 200 k scl_sink sda_sink ddc_en (0 v to 3.3 v) scl_source sda_source out_d2? out_d2+ in_d2? in_d2+ out_d3? out_d3+ in_d3? in_d3+ out_d4? out_d4+ in_d4? in_d4+ ptn3300a oe_n enable enable enable enable input bias 50 50 input bias 50 50 input bias 50 50 enable enable enable enable ddc level shifter ptn3300b block diagram 002aad682 out_d1? out_d1+ input bias 50 50 in_d1? in_d1+ hpd level shifter hpd_source (0 v to 3.3 v) hpd_sink (0 v to 5 v) 200 k scl_sink sda_sink ddc_en (0 v to 3.3 v) scl_source sda_source out_d2? out_d2+ in_d2? in_d2+ out_d3? out_d3+ in_d3? in_d3+ out_d4? out_d4+ in_d4? in_d4+ ptn3300b oe_n enable enable enable enable input bias 50 50 input bias 50 50 input bias 50 50 enable enable enable enable ddc level shifter
ptn3300a pinout diagram (hwqfn48r and hwqfn48) ptn3300b pinout diagram (hwqfn48r and hwqfn48) ptn3301 pinout diagram (hwqfn48r and hwqfn48) ptn3301 block diagram 002aad345 out_d1? out_d1+ input bias 50 50 in_d1? in_d1+ hpd level shifter hpd_source (0 v to 3.3 v) hpd_sink (0 v to 5 v) 200 k scl_sink sda_sink ddc_en (0 v to 3.3 v) scl_source sda_source out_d2? out_d2+ in_d2? in_d2+ out_d3? out_d3+ in_d3? in_d3+ out_d4? out_d4+ in_d4? in_d4+ ptn3301 oe_n enable enable enable enable input bias 50 50 input bias 50 50 input bias 50 50 enable enable enable enable ddc buffer and level shifter i 2 c-bus slave rom ddet ptn3301 the ptn3301 is the same as the ptn3300b, but with additional features for hdmi applications. it has actively buffered ddc lines that meet hdmis more stringent specifcations for capacitive loading, and, in accordance with the displayport interoperability guidelines, is capable of responding to an i 2 c-based query to detect an hdmi dongle via the ddc channel. all the level shifters are available in a very thin, 48-pin hwqfnr (7 x 7 x 0.7 mm) or a 48-pin hwqfn (7 x 7 x 0.65 mm) package. all operate from a 3.3-v power supply, and save power by using active pin control and automatic control via hot-plug detection. when there is no monitor actively connected to the device, the device automatically goes into idle mode and consumes only a negligible amount of supply current. for more information visit www.nxp.com/displayport out_d4+ out_d4? v dd out_d3+ out_d3? gnd out_d2+ out_d2? v dd out_d1+ out_d1? gnd v dd gnd n.c. scl_source sda_source hpd_source_n rext gnd n.c. n.c. v dd gnd in_d4+ in_d4? v dd in_d3+ in_d3? gnd in_d2+ in_d2? v dd in_d1+ in_d1? gnd 002aad647 oe_n v dd gnd scl_sink sda_sink hpd_sink gnd ddc_en v dd n.c. n.c. gnd ptn3300ahf 12 25 11 26 10 27 9 28 8 29 7 30 6 31 5 32 4 33 3 34 2 35 1 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 terminal 1 index area transparent top view out_d4+ out_d4? v dd out_d3+ out_d3? gnd out_d2+ out_d2? v dd out_d1+ out_d1? gnd v dd gnd n.c. scl_source sda_source hpd_source rext gnd n.c. n.c. v dd gnd in_d4+ in_d4? v dd in_d3+ in_d3? gnd in_d2+ in_d2? v dd in_d1+ in_d1? gnd 002aad683 oe_n v dd gnd scl_sink sda_sink hpd_sink gnd ddc_en v dd n.c. n.c. gnd ptn3300bhf 12 25 11 26 10 27 9 28 8 29 7 30 6 31 5 32 4 33 3 34 2 35 1 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 terminal 1 index area transparent top view in_d4+ in_d4? v dd in_d3+ in_d3? gnd in_d2+ in_d2? v dd in_d1+ in_d1? gnd oe_n v dd gnd scl_sink sda_sink hpd_sink gnd dcc_en v dd n.c. n.c. gnd out_d4+ out_d4? v dd out_d3+ out_d3? gnd out_d2+ out_d2? v dd out_d1+ out_d1? gnd v dd gnd n.c. scl_source sda_source hpd_source rext gnd ddet n.c. v dd gnd 002aad346 ptn3301hf 12 25 11 26 10 27 9 28 8 29 7 30 6 31 5 32 4 33 3 34 2 35 1 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 terminal 1 index area transparent top view
www.nxp.com ? 2008 nxp b.v. all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. date of release: march 2008 document order number: 9397 750 16192 printed in the usa feature ptn3300 ptn3300a ptn3300b ptn3301 data rate per lane 1.65 gbps 2.25 gbps 2.25 gbps 2.25 gbps tmds level shifters ? ? ? ? ddc active buffer / level shifter ? ddc passive level shifter ? ? ? hpd level shifter 3.3-v, non-inverting 1.1-v, inverting 3.3-v, non-inverting 3.3-v, non-inverting automatic standby mode upon hpd_sink = low ? ? ? ? interchangeable tmds data and clock lanes ? ? ? ? responds to i 2 c-bus hdmi dongle detection optional applications dvi motherboard, dongle dvi, hdmi motherboard dvi, hdmi motherboard, dongle dvi, hdmi motherboard, dongle selection guide ordering information type number package type dimensions package feature ptn3300hf hwqfn48r 7 x 7 x 0.7 mm non-wraparound terminals ptn3300ahf hwqfn48r 7 x 7 x 0.7 mm non-wraparound terminals ptn3300bhf hwqfn48r 7 x 7 x 0.7 mm non-wraparound terminals ptn3301hf hwqfn48r 7 x 7 x 0.7 mm non-wraparound terminals ptn3300ahf2 hwqfn48 7 x 7 x 0.65 mm wrap-around terminals ptn3300bhf2 hwqfn48 7 x 7 x 0.65 mm wrap-around terminals PTN3301HF2 hwqfn48 7 x 7 x 0.65 mm wrap-around terminals
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